linux-kernel - Re: [RFC PATCH 2/8] jump label v4 - x86: Introduce generic jump patching without stop

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Message-ID: <4B54D01C.1070505@zytor.com>
Date:	Mon, 18 Jan 2010 13:18:20 -0800
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Masami Hiramatsu <mhiramat@...hat.com>
CC:	Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca>,
	Arjan van de Ven <arjan@...radead.org>,
	rostedt@...dmis.org, Jason Baron <jbaron@...hat.com>,
	linux-kernel@...r.kernel.org, mingo@...e.hu, tglx@...utronix.de,
	andi@...stfloor.org, roland@...hat.com, rth@...hat.com
Subject: Re: [RFC PATCH 2/8] jump label v4 - x86: Introduce generic jump	patching
 without stop_machine

On 01/18/2010 12:53 PM, Masami Hiramatsu wrote:
>>
>> This is utter and complete nonsense.   You seem to think that everything
>> is guaranteed to hit the breakpoint, which is obviously false.
>> Furthermore, until you have done the serialization, you're not
>> guaranteed the *breakpoint* is seen, so you have the same condition.
> 
> In that time frame, I guess that the processor sees non-modified
> instruction and executes it. Since we'll wait until serializing on
> each processor, I think it is OK for int3-bypass method.
> 
> (Of course, this can depend on chip, it is possible that there is a chip
>  which causes a fault when it has a cache-discarding signal on current-
>  instruction decoding slot. That's also why we are asking this method
>  is OK for x86 processors.)
> 

Yes, it is possible, however, if that was the case, then int3 wouldn't
work either.  As I said, to the best of our knowledge, at least Intel
processors are okay for a single-byte update (I will wait to try to
state the full general rule until it has been officially approved or
killed.)

	-hpa

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