lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 27 Jan 2010 17:43:45 -0800
From:	Abhijeet Dharmapurikar <adharmap@...eaurora.org>
To:	Russell King - ARM Linux <linux@....linux.org.uk>
CC:	linux-arm-kernel@...ts.infradead.org, Ingo Molnar <mingo@...e.hu>,
	Catalin Marinas <catalin.marinas@....com>,
	Yinghai Lu <yinghai@...nel.org>,
	Tony Lindgren <tony@...mide.com>,
	Santosh Shilimkar <santosh.shilimkar@...com>,
	Kevin Hilman <khilman@...prootsystems.com>,
	Kalle Valo <kalle.valo@....fi>, Jean Pihet <jpihet@...sta.com>,
	Linus Walleij <linus.walleij@...ricsson.com>,
	Colin Tuckley <colin.tuckley@....com>,
	Philby John <pjohn@...mvista.com>,
	Srinidhi Kasagar <srinidhi.kasagar@...ricsson.com>,
	Alessandro Rubini <rubini@...pv.it>,
	Andrea Gallo <andrea.gallo@...ricsson.com>,
	linux-kernel@...r.kernel.org, linux-omap@...r.kernel.org,
	Abhijeet Dharmapurikar <adharmap@...cinc.com>,
	linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH 3/5] gic: Add set_type callback

Russell King - ARM Linux wrote:
> On Wed, Jan 27, 2010 at 11:32:27AM -0800, adharmap@...eaurora.org wrote:
>> +	if (flow_type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) {
>> +		reg_value |= (2<<bit_index);
>> +		writel(reg_value, gic_dist_base(irq) + GIC_DIST_CONFIG
>> +							+ register_index);
>> +		__set_irq_handler_unlocked(irq, handle_edge_irq);
>> +	}
>> +
>> +	if (flow_type & (IRQ_TYPE_LEVEL_HIGH|IRQ_TYPE_LEVEL_LOW)) {
> 
> This is actually where things start to get rather sticky - because
> there may well be on-chip inverters between the GIC and external
> peripherals.
Actually the comment in gic_dist_init mentions about configuring SPI's 
as level low when the GIC only supports level high. That suggests 
presence of an inverter.
> 
> Since the GIC can only sense one edge or one level depending on the
> hardware setup, it seems wrong to allow the configuration of both
> high and low levels, and both edges.
Agree, but this change at least lets us configure them as edge/level 
triggered.

One solution (a rather easy one) is we simply reject LEVEL_LOW and 
EDGE_FALLING and think as if the inverters belong to the peripherals 
rather than the GIC.

Please suggest alternative implementation ideas.





--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ