linux-kernel - Re: USB mass storage and ARM cache coherency

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Message-ID: <Pine.LNX.4.44L0.1002011512060.1368-100000@iolanthe.rowland.org>
Date:	Mon, 1 Feb 2010 15:14:04 -0500 (EST)
From:	Alan Stern <stern@...land.harvard.edu>
To:	Catalin Marinas <catalin.marinas@....com>
cc:	Matthew Dharm <mdharm-kernel@...-eyed-alien.net>,
	Sergei Shtylyov <sshtylyov@...mvista.com>,
	Ming Lei <tom.leiming@...il.com>, <linux-usb@...r.kernel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	Sebastian Siewior <bigeasy@...utronix.de>,
	Greg KH <greg@...ah.com>
Subject: Re: USB mass storage and ARM cache coherency

On Mon, 1 Feb 2010, Catalin Marinas wrote:

> On Fri, 2010-01-29 at 18:54 +0000, Matthew Dharm wrote:
> > HOWEVER, I firmly believe that the cache-management functions belong with
> > the driver that actually talks to the low-level hardware, as that's the
> > only place where you can be 100% certain of what cache operations are
> > needed.  After all, I think someone is working on a USB-over-IP transport,
> > and trying to manage cache at the usb-storage level in that scenario is
> > just silly.
> > 
> > So, let's put this in the HCD drivers and be done with it.
> 
> The patch below is what fixes the I-D cache incoherency issues on ARM. I
> don't particularly like the solution but it seems to be the only one
> available.
> 
> IMHO, Linux should have functions similar to the DMA API but for PIO
> drivers (e.g. pio_map_single/pio_unmap_single) that non-coherent
> architectures can define, otherwise being no-ops. Any thoughts?

You should bring this up on the linux-arm-kernel mailing list and CC:  
the ARM maintainer.  They are the ones most directly affected.

Alan Stern

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