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Message-ID: <bd4cb8901002031551h3f1edb2bj706c768344fcd93f@mail.gmail.com>
Date:	Thu, 4 Feb 2010 00:51:30 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	Ingo Molnar <mingo@...e.hu>, Paul Mackerras <paulus@...ba.org>,
	"Metzger, Markus T" <markus.t.metzger@...el.com>,
	lkml <linux-kernel@...r.kernel.org>,
	Robert Richter <robert.richter@....com>,
	"David S. Miller" <davem@...emloft.net>,
	Jamie Iles <jamie.iles@...ochip.com>,
	Paul Mundt <lethal@...ux-sh.org>,
	Arjan van de Ven <arjan@...radead.org>,
	"H. Peter Anvin" <hpa@...or.com>, perfmon2-devel@...ts.sf.net
Subject: Re: [RFC][PATCH] perf_events, x86: PEBS support

On Thu, Feb 4, 2010 at 12:50 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Wed, 2010-02-03 at 15:40 +0100, Peter Zijlstra wrote:
>>
>> If only they would reset the counter on overflow instead of on record,
>> that would solve quite a few issues I imagine.
>
> So I tried enabling the regular PMC overflow interrupt and reprogramming
> the counter from that, but touching the counter seems to destroy the
> PEBS assist, so much for that idea.
>
Yes, you have to leave the INT bit off, otherwise you get an
interrupt for each overflow, thus you lose the buffer advantage.
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