[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <bd4cb8901002040704vcd2d8feo82e2e1c166a02669@mail.gmail.com>
Date: Thu, 4 Feb 2010 16:04:17 +0100
From: Stephane Eranian <eranian@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: linux-kernel@...r.kernel.org, mingo@...e.hu, paulus@...ba.org,
davem@...emloft.net, fweisbec@...il.com, robert.richter@....com,
perfmon2-devel@...ts.sf.net, eranian@...il.com
Subject: Re: [PATCH] perf_events: AMD event scheduling (v2)
On Thu, Feb 4, 2010 at 3:59 PM, Peter Zijlstra <peterz@...radead.org> wrote:
>
> On Thu, 2010-02-04 at 15:55 +0100, Peter Zijlstra wrote:
> > > + if (boot_cpu_data.x86_max_cores < 2)
> > > + return;
> >
> > So there are no single core AMD chips that have a NorthBridge PMU? What
> > about the recent 64bit single core laptop chips?
>
> D'0h, for those there is no need to create inter-cpu constraints.
>
Exactly!
--
Stephane Eranian | EMEA Software Engineering
Google France | 38 avenue de l'Opéra | 75002 Paris
Tel : +33 (0) 1 42 68 53 00
This email may be confidential or privileged. If you received this
communication by mistake, please
don't forward it to anyone else, please erase all copies and
attachments, and please let me know that
it went to the wrong person. Thanks
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists