linux-kernel - RE: [perfmon2] [PATCH] perf_events: AMD event scheduling (v3)

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Message-ID: <6096959DEF5C9447A6BF80BDC7EB9EDC14913E8B@SBOSEXMB1.amd.com>
Date:	Wed, 10 Feb 2010 10:59:24 -0500
From:	"Drongowski, Paul" <paul.drongowski@....com>
To:	<eranian@...il.com>, "Peter Zijlstra" <peterz@...radead.org>
CC:	<perfmon2-devel@...ts.sf.net>, <fweisbec@...il.com>,
	<linux-kernel@...r.kernel.org>,
	"Stephane Eranian" <eranian@...gle.com>, <paulus@...ba.org>,
	<mingo@...e.hu>, <davem@...emloft.net>
Subject: RE: [perfmon2] [PATCH] perf_events: AMD event scheduling (v3)

Good catch!

Historically, AMD has treated the bit field EventSelect<7:5>
in model specific register MSRC001_00[03:00] Performance Event
Select Register (PERF_CTL[3:0]) like an "event group selector".
Please see the "BIOS and Kernel Developer's Guide for AMD
Family 10h Processors."

Typically, EventSelect<7:5> == 0x7 selects Northbridge
events.

Yes, when the event select value was extended to twelve bits,
it placed this field somewhere in the middle of the full
twelve bit value. ;-)

Please consider AMD Family 10h event 0x1C0 Retired x87
Floating Point Operations. This is not a Northbridge event.
If the test is greater than or equal to (e.g., 0x1C0 >= 0x0E0),
then this event will be incorrectly identified as a
Northbridge event. (There are other similar examples.)

So, I would recommend testing EventSelect<7:5> == 0x7
in order to detect AMD Northbridge events.

Thanks for implementing the AMD event scheduling feature!

-- pj

Paul Drongowski
AMD CodeAnalyst team


-----Original Message-----
From: stephane eranian [mailto:eranian@...glemail.com] 
Sent: Wednesday, February 10, 2010 8:58 AM
To: Peter Zijlstra
Cc: perfmon2-devel@...ts.sf.net; fweisbec@...il.com; linux-kernel@...r.kernel.org; Stephane Eranian; paulus@...ba.org; mingo@...e.hu; davem@...emloft.net
Subject: Re: [perfmon2] [PATCH] perf_events: AMD event scheduling (v3)

On Wed, Feb 10, 2010 at 2:28 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Wed, 2010-02-10 at 14:17 +0100, Peter Zijlstra wrote:
>> On Wed, 2010-02-10 at 14:04 +0100, Stephane Eranian wrote:
>>
>> > > @@ -2268,7 +2268,7 @@ static inline int amd_is_nb_event(struct
>> > >        u64 val = hwc->config & K7_EVNTSEL_EVENT_MASK;
>> > >        /* event code : bits [35-32] | [7-0] */
>> > >        val = (val >> 24) | (val & 0xff);
>> > > -       return val >= 0x0e0;
>> > > +       return val >= 0xe00;
>> > >  }
>> > >
>> > I don't understand the change from 0xe0 to 0xe00.
>> > That's not the same thing at all.
>> > Event select is bits 0-7 + 32-35.
>>
>> OK that appears to be my bad, because you extended K7_EVNTSEL_EVENT_MASK
>> with bit 35 I thought NB events all had bit 35 set.
>>
>> But looking at the AMD docs it does indeed appear to start at 0xe0, and
>> there are no events with bit 35 set, only a few with bit 32.
>>
>> I'll switch it back to 0xe0.
>
> Fwiw, for the purpose of that function you might as well write:
>
> static inline int amd_is_nb_event(struct hw_perf_event *hwc)
> {
>        return (hwc->config & K7_EVNTSEL_EVENT_MASK) > 0xe0;
> }
>
> No need to move bits around higher than the value you compare against.
>
I think given the existing event codes, that would be fine too.

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