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Message-ID: <SNT125-W34AEECE0C00025B544A35C3490@phx.gbl>
Date: Mon, 15 Feb 2010 16:30:51 -0800
From: Yuhong Bao <yuhongbao_386@...mail.com>
To: <macro@...ux-mips.org>, <sassmann@...e.de>
CC: <ebiederm@...ssion.com>, <od@...e.de>, <tglx@...utronix.de>,
<mingo@...e.hu>, <hpa@...or.com>, <jonathan@...masters.org>,
<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 0/7] Boot IRQ quirks and rerouting
> Well, this is clear these chipsets are broken beyond imagination,
> negating some 15 years of I/O APIC compatibility where masking an input in
> its redirection table is expected not to have any side effects. They
> should have used a separate bit for the legacy INTx redirection. That has
> been fixed in hardware though and there is nothing we can do about it at
> this stage. Hire competent hardware designers the next time.
I think part of it has to do with how chipset vendors integrated the first I/O APIC into the southbridge around 1999-2001 (Intel was first to do so back in 1999, I think), which were necessary if there were any hope of putting them in uniprocessor systems. Unfortunately, the way it was integrated, the interrupt pins that goes outside the southbridge was shared with both the 8259 PICs (via a PIR) AND the first I/O APIC, and there was no way to do otherwise. While that was very convenient for single I/O APIC systems, on multiple I/O APIC systems it can cause boot interrupts to be delivered to the first I/O APIC as well as the PIC which could be very bad, as you have seen.
Yuhong Bao
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