linux-kernel - Re: USB mass storage and ARM cache coherency

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Message-ID: <4B7BBD7D.9090602@warmcat.com>
Date:	Wed, 17 Feb 2010 10:57:17 +0100
From:	Andy Green <andy@...mcat.com>
To:	Sascha Hauer <s.hauer@...gutronix.de>
CC:	Catalin Marinas <catalin.marinas@....com>,
	Matthew Dharm <mdharm-kernel@...-eyed-alien.net>,
	Sergei Shtylyov <sshtylyov@...mvista.com>,
	Ming Lei <tom.leiming@...il.com>,
	Sebastian Siewior <bigeasy@...utronix.de>,
	linux-usb@...r.kernel.org,
	linux-kernel <linux-kernel@...r.kernel.org>,
	Pavel Machek <pavel@....cz>, Greg KH <greg@...ah.com>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: USB mass storage and ARM cache coherency

On 02/17/10 10:50, Somebody in the thread at some point said:
> On Mon, Feb 08, 2010 at 11:03:14AM +0100, Andy Green wrote:
>> On 02/08/10 10:51, Somebody in the thread at some point said:
>>
>>> We could of course flush the caches every time we get a page fault but
>>> that's far from optimal, especially since DMA-capable drivers to do not
>>> pollute the D-cache and don't need this extra flushing. Note that the
>>> recent ARM processors have PIPT caches but separate for I and D and it's
>>> the PIO drivers that pollute the D-cache.
>>
>> Just noting that AFAIK iMX31 USB and MMC drivers both are PIO at the
>> moment, for lack of any platform DMA support of its unusual DMA engine.
>
> The EHCI module has its own DMA engine and has nothing to do with the
> SDMA engine.

You're right, my mistake.  iMX31 MMC is PIO due to no SDMA support though.

-Andy
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