linux-kernel - [PATCH 10/10] x86-32: panic on !CX8 && XMM

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Message-Id: <1266406962-17463-11-git-send-email-luca@luca-barbieri.com>
Date:	Wed, 17 Feb 2010 12:42:42 +0100
From:	Luca Barbieri <luca@...a-barbieri.com>
To:	mingo@...e.hu
Cc:	hpa@...or.com, a.p.zijlstra@...llo.nl, akpm@...ux-foundation.org,
	linux-kernel@...r.kernel.org,
	Luca Barbieri <luca@...a-barbieri.com>
Subject: [PATCH 10/10] x86-32: panic on !CX8 && XMM

No known CPU should have this combination, and future ones are very
unlikely to.

However, should this happen, we would generate working but non-atomic
code, so panic instead.
---
 arch/x86/lib/atomic64_32.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/x86/lib/atomic64_32.c b/arch/x86/lib/atomic64_32.c
index 9ff8589..35dbd12 100644
--- a/arch/x86/lib/atomic64_32.c
+++ b/arch/x86/lib/atomic64_32.c
@@ -47,6 +47,17 @@ EXPORT_SYMBOL(cx8_atomic64_inc_not_zero_cx8call);
 union generic_atomic64_lock generic_atomic64_lock[ATOMIC64_NR_LOCKS] __cacheline_aligned_in_smp;
 pure_initcall(init_generic_atomic64_lock);
 
+static int __init panic_on_sse_without_cx8(void)
+{
+	/* no known CPU should do this, and we generate non-atomic code in this case
+	 * because we mix the generic spinlock-reliant code and the SSE code
+	 */
+	if (!boot_cpu_has(X86_FEATURE_CX8) && boot_cpu_has(X86_FEATURE_XMM))
+		panic("CPUs without CX8 but with SSE are not supported\nBoot with clearcpuid=25 and report your CPU model to linux-kernel@...r.kernel.org\n");
+	return 0;
+}
+core_initcall(panic_on_sse_without_cx8);
+
 EXPORT_SYMBOL(generic_atomic64_add);
 EXPORT_SYMBOL(generic_atomic64_add_return);
 EXPORT_SYMBOL(generic_atomic64_sub);
-- 
1.6.6.1.476.g01ddb

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