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Message-ID: <bd4cb8901003111309q57e9e2efo37bd4bc9057216b2@mail.gmail.com>
Date:	Thu, 11 Mar 2010 13:09:26 -0800
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	linux-kernel@...r.kernel.org, mingo@...e.hu, paulus@...ba.org,
	fweisbec@...il.com, robert.richter@....com, davem@...emloft.net,
	perfmon2-devel@...ts.sf.net
Subject: Re: [PATCH] perf_events: remove bogus Intel Core constraint on 
	ITLB_MISS_RETIRED

On Thu, Mar 11, 2010 at 1:07 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Thu, 2010-03-11 at 12:59 -0800, eranian@...gle.com wrote:
>> Contrary to what Vol3b section 30.4.3 leads to believe, there is
>> no constraint on ITLB_MISS_RETIRED on Intel Core-based CPU, so
>> remove it.
>
> Is that from Intel, and will they clarify the text in the next version
> of the document?
>
Yes.

>> Signed-off-by: Stephane Eranian <eranian@...gle.com>
>> --
>>  perf_event_intel.c |    1 -
>>  1 file changed, 1 deletion(-)
>> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
>> index 971dc6e..58e83cd 100644
>> --- a/arch/x86/kernel/cpu/perf_event_intel.c
>> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
>> @@ -43,7 +43,6 @@ static struct event_constraint intel_core2_event_constraints[] =
>>       INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
>>       INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
>>       INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
>> -     INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
>>       INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
>>       EVENT_CONSTRAINT_END
>>  };
>
>
>
>



-- 
Stephane Eranian  | EMEA Software Engineering
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