linux-kernel - Re: [patch] x86: handle legacy PIC interrupts on all the cpu's

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Message-ID: <4B9EABE8.1020203@kernel.org>
Date:	Mon, 15 Mar 2010 14:51:36 -0700
From:	Yinghai Lu <yinghai@...nel.org>
To:	Suresh Siddha <suresh.b.siddha@...el.com>
CC:	Ingo Molnar <mingo@...e.hu>, "H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	LKML <linux-kernel@...r.kernel.org>,
	"Eric W. Biederman" <ebiederm@...ssion.com>
Subject: Re: [patch] x86: handle legacy PIC interrupts on all the cpu's

On 03/15/2010 03:33 PM, Suresh Siddha wrote:
> Ingo Molnar reported that with the recent changes of not statically blocking
> IRQ0_VECTOR..IRQ15_VECTOR's on all the cpu's, broke an AMD platform
> (with Nvidia chipset) boot when "noapic" boot option is used.
> 
> On this platform, legacy PIC interrupts are getting delivered to all the
> cpu's instead of just the boot cpu. Thus not initializing the vector to irq
> mapping for the legacy irq's resulted in not handling certain interrupts
> causing boot hang.
> 
> Fix this by initializing the vector to irq mapping on all the logical cpu's,
> if the legacy IRQ is handled by the legacy PIC.
> 
> Reported-by: Ingo Molnar <mingo@...e.hu>
> Signed-off-by: Suresh Siddha <suresh.b.siddha@...el.com>
> ---
> 
> diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
> index a929c9e..46c0fe0 100644
> --- a/arch/x86/include/asm/hw_irq.h
> +++ b/arch/x86/include/asm/hw_irq.h
> @@ -133,6 +133,7 @@ extern void (*__initconst interrupt[NR_VECTORS-FIRST_EXTERNAL_VECTOR])(void);
>  
>  typedef int vector_irq_t[NR_VECTORS];
>  DECLARE_PER_CPU(vector_irq_t, vector_irq);
> +extern void setup_vector_irq(int cpu);
>  
>  #ifdef CONFIG_X86_IO_APIC
>  extern void lock_vector_lock(void);
> diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
> index e4e0ddc..10f0a1a 100644
> --- a/arch/x86/kernel/apic/io_apic.c
> +++ b/arch/x86/kernel/apic/io_apic.c
> @@ -1268,6 +1268,14 @@ void __setup_vector_irq(int cpu)
>  	/* Mark the inuse vectors */
>  	for_each_irq_desc(irq, desc) {
>  		cfg = desc->chip_data;
> +
> +		/*
> +		 * If it is a legacy IRQ handled by the legacy PIC, this cpu
> +		 * will be part of the irq_cfg's domain.
> +		 */
> +		if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
> +			cpumask_set_cpu(cpu, cfg->domain);
> +
>  		if (!cpumask_test_cpu(cpu, cfg->domain))
>  			continue;
>  		vector = cfg->vector;
> diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
> index ef257fc..daaf413 100644
> --- a/arch/x86/kernel/irqinit.c
> +++ b/arch/x86/kernel/irqinit.c
> @@ -141,6 +141,27 @@ void __init init_IRQ(void)
>  	x86_init.irqs.intr_init();
>  }
>  
> +/*
> + * Setup the vector to irq mappings.
	> + */
> +void setup_vector_irq(int cpu)
> +{
> +	int irq;
> +
> +	/*
> +	 * On most of the platforms, legacy PIC delivers the interrupts on the
> +	 * boot cpu. But there are certain platforms where PIC interrupts are
> +	 * delivered to multiple cpu's. If the legacy IRQ is handled by the
> +	 * legacy PIC, for the new cpu that is coming online, setup the static
> +	 * legacy vector to irq mapping.
> +	 */
> +	for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
> +		if (!IO_APIC_IRQ(irq))
> +			per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;

seems those three lines are not needed...



YH
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