linux-kernel - Re: [PATCH] KVM MMU: check reserved bits only if CR4.PSE=1 or CR4.PAE=1

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Message-ID: <4B9F2A54.9020505@cn.fujitsu.com>
Date:	Tue, 16 Mar 2010 14:51:00 +0800
From:	Xiao Guangrong <xiaoguangrong@...fujitsu.com>
To:	Avi Kivity <avi@...hat.com>
CC:	Sheng Yang <sheng@...ux.intel.com>,
	Marcelo Tosatti <mtosatti@...hat.com>,
	LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] KVM MMU: check reserved bits only if CR4.PSE=1 or CR4.PAE=1

Avi Kivity wrote:
> On 03/16/2010 08:03 AM, Xiao Guangrong wrote:
>>
>>> I think the only change is that is !is_pse(vcpu) we ignore bit 7?
>>>      
>> If the vcpu is in PT32E_ROOT_LEVEL/PT64_ROOT_LEVEL mode, CR4.PAE
>> is aways enabled, so what we need do is ignore bit7 if !is_pse(vcpu)
>> under PT32_ROOT_LEVEL mode, right?
>>    
> 
> I think PAE will fault if bit7 is set and !is_pse(vcpu), but not sure.

Quote AMD's specification:
The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses
the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte
page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored
by PAE paging.

Quote Intel's specification:
When PAE is enabled, the 2-MByte page size is selected by setting the page size (PS)
flag in a page-directory entry (see Figure 3-14). (As shown in Table 3-3, the PSE flag
in control register CR4 has no affect on the page size when PAE is enabled.)

So i think PAE just ignore CR4.PSE

Thanks,
Xiao
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