linux-kernel - Re: [RFC][PATCH 2/2] x86,perf: add cache events in p4 PMU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20100318160135.GD5062@lenovo>
Date:	Thu, 18 Mar 2010 19:01:35 +0300
From:	Cyrill Gorcunov <gorcunov@...il.com>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	Lin Ming <ming.m.lin@...el.com>,
	Peter Zijlstra <peterz@...radead.org>,
	lkml <linux-kernel@...r.kernel.org>
Subject: Re: [RFC][PATCH 2/2] x86,perf: add cache events in p4 PMU

On Thu, Mar 18, 2010 at 04:56:10PM +0100, Ingo Molnar wrote:
> 
> * Lin Ming <ming.m.lin@...el.com> wrote:
> 
> > Add cache events in p4 PMU.
> > 
> > Move the HT bit setting code from p4_pmu_event_map to p4_hw_config.
> > So the cache events can get HT bit set correctly.
> > 
> > Tested on my P4 desktop, below 6 cache events work.
> > L1-dcache-load-misses
> > LLC-load-misses
> > dTLB-load-misses
> > dTLB-store-misses
> > iTLB-loads
> > iTLB-load-misses
> > 
> > Signed-off-by: Lin Ming <ming.m.lin@...el.com>
> > ---
> >  arch/x86/include/asm/msr-index.h     |    2 +
> >  arch/x86/include/asm/perf_event_p4.h |   10 ++
> >  arch/x86/kernel/cpu/perf_event_p4.c  |  153 ++++++++++++++++++++++++++++++++--
> >  3 files changed, 159 insertions(+), 6 deletions(-)
> 
> i tried it on a Pentium-D box, and it works pretty well:
> 
> rhea:/home/mingo/tip> perf stat -a sleep 1
> 
>  Performance counter stats for 'sleep 1':
> 
>     2003.237268  task-clock-msecs         #      2.000 CPUs 
>              11  context-switches         #      0.000 M/sec
>               2  CPU-migrations           #      0.000 M/sec
>             174  page-faults              #      0.000 M/sec
>           47361  cycles                   #      0.024 M/sec  (scaled from 52.83%)
>             430  instructions             #      0.009 IPC    (scaled from 74.58%)
>           23873  branches                 #      0.012 M/sec  (scaled from 96.70%)
>             193  branch-misses            #      0.808 %      (scaled from 49.64%)
>             867  cache-references         #      0.000 M/sec  (scaled from 49.69%)
>             504  cache-misses             #      0.000 M/sec  (scaled from 49.58%)
> 
>     1.001411586  seconds time elapsed
> 
> So i've applied your patches. Cyrill, what do you think?

Sorry for a bit delay, yes, pick it up please. I found that we have an
issue in escr binding (which is pretty mine error), hope to fix it up
today. Also I hope to eventually implement raw events this weekend
but better to base the new code on all this stuff merged. This will
allow to "take a look" on code structure from a high point and find
potential caveats.

All-in-one

Reviewed-by: Cyrill Gorcunov <gorcunov@...nvz.org>

Thanks a huge, Ming!

> 
> 	Ingo
> 
	-- Cyrill
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/