linux-kernel - [tip:perf/core] x86, perf: Fix few cosmetic dabs for P4 pmu (comments and constantify)

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Message-ID: <tip-9c8c6bad3137112d2c7bf3d215b736ee4215fa74@git.kernel.org>
Date:	Thu, 18 Mar 2010 22:03:54 GMT
From:	tip-bot for Cyrill Gorcunov <gorcunov@...il.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
	gorcunov@...nvz.org, ming.m.lin@...el.com, tglx@...utronix.de,
	gorcunov@...il.com, mingo@...e.hu
Subject: [tip:perf/core] x86, perf: Fix few cosmetic dabs for P4 pmu (comments and constantify)

Commit-ID:  9c8c6bad3137112d2c7bf3d215b736ee4215fa74
Gitweb:     http://git.kernel.org/tip/9c8c6bad3137112d2c7bf3d215b736ee4215fa74
Author:     Cyrill Gorcunov <gorcunov@...il.com>
AuthorDate: Fri, 19 Mar 2010 00:12:56 +0300
Committer:  Ingo Molnar <mingo@...e.hu>
CommitDate: Thu, 18 Mar 2010 22:17:46 +0100

x86, perf: Fix few cosmetic dabs for P4 pmu (comments and constantify)

- A few ESCR have escaped fixing at previous attempt.
- p4_escr_map is read only, make it const.

Nothing serious.

Signed-off-by: Cyrill Gorcunov <gorcunov@...nvz.org>
Cc: Lin Ming <ming.m.lin@...el.com>
LKML-Reference: <20100318211256.GH5062@...ovo>
Signed-off-by: Ingo Molnar <mingo@...e.hu>
---
 arch/x86/include/asm/perf_event_p4.h |    4 ++--
 arch/x86/kernel/cpu/perf_event_p4.c  |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 871249c..2a1a57f 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -401,13 +401,13 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
 #define P4_RETIRED_MISPRED_BRANCH_TYPE	P4_EVENT_PACK(0x05, 0x02)
 	/*
 	 * MSR_P4_TBPU_ESCR0:	4, 5
-	 * MSR_P4_TBPU_ESCR0:	6, 7
+	 * MSR_P4_TBPU_ESCR1:	6, 7
 	 */
 
 #define P4_RETIRED_BRANCH_TYPE		P4_EVENT_PACK(0x04, 0x02)
 	/*
 	 * MSR_P4_TBPU_ESCR0:	4, 5
-	 * MSR_P4_TBPU_ESCR0:	6, 7
+	 * MSR_P4_TBPU_ESCR1:	6, 7
 	 */
 
 #define P4_RESOURCE_STALL		P4_EVENT_PACK(0x01, 0x01)
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index b7bf991..b8a811a 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -545,7 +545,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
 }
 
 /* ESCRs are not sequential in memory so we need a map */
-static unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {
+static const unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {
 	MSR_P4_ALF_ESCR0,	/*  0 */
 	MSR_P4_ALF_ESCR1,	/*  1 */
 	MSR_P4_BPU_ESCR0,	/*  2 */
--
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