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Date:	Wed, 24 Mar 2010 06:32:57 +0100
From:	Andi Kleen <>
Subject: [PATCH] Allow Intel platforms to declare unsynchronized TSC to

Allow Intel platforms to declare unsynchronized TSC to kernel

[This came out of a private discussion with Linus last week]

Nehalem class processors support the CONSTANT_TSC bit in the 8000_0007 CPUID
leaf to declare CONSTANT_TSC. One of the ideas behind this bit was to allow the 
platform to clear it when it cannot guarantee a constant TSC.

Unfortunately this doesn't work right now because the Intel CPU
initialization also checks the model number and assumes that
all CPUs newer than Yonah have CONSTANT_TSC too.

Terminate the model number check before Nehalem and rely on the 8000_0007
bit only on newer CPUs. This way the platform can actually turn it off.

Atom CPUs might also have newer model numbers and do not necessarily
have that bit, but they are all single socket and expected to always
have synchronous TSCs.

Open: the two checks still differ in setting sched_clock_stable. 

Signed-off-by: Andi Kleen <>

 arch/x86/kernel/cpu/intel.c |   11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

Index: linux-2.6.34-rc1-ak/arch/x86/kernel/cpu/intel.c
--- linux-2.6.34-rc1-ak.orig/arch/x86/kernel/cpu/intel.c	2010-03-03 02:01:27.000000000 +0100
+++ linux-2.6.34-rc1-ak/arch/x86/kernel/cpu/intel.c	2010-03-24 06:16:42.000000000 +0100
@@ -43,8 +43,16 @@
+	/*
+	 * On Nehalem+ class we trust the CONSTANT_TSC bit in 8000_0007 edx,
+	 * so that a platform that doesn't have synchronized TSCs can clear it.
+ 	 * Older CPUs didn't set that bit, so we keep hard coding the model
+	 * numbers for those.
+ 	 * Note this matches Atom class too, but there the TSCs are always
+	 * synchronized anyways.
+ 	 */
 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
-		(c->x86 == 0x6 && c->x86_model >= 0x0e))
+		(c->x86 == 0x6 && c->x86_model >= 0x0e && c->x86_model < 0x1a))
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 #ifdef CONFIG_X86_64
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