linux-kernel - Re: [PATCH] x86, MCE, fix MSR_IA32_MCI

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Message-ID: <1269852015.1060.102.camel@yhuang-dev.sh.intel.com>
Date:	Mon, 29 Mar 2010 16:40:15 +0800
From:	Huang Ying <ying.huang@...el.com>
To:	Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
Cc:	Ingo Molnar <mingo@...e.hu>, "H. Peter Anvin" <hpa@...or.com>,
	Andi Kleen <ak@...ux.intel.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI threshold setup

Hi, Seto san,

Thanks for review.

On Mon, 2010-03-29 at 16:26 +0800, Hidetoshi Seto wrote:
> (2010/03/29 16:16), Huang Ying wrote:
> > It is reported that CMCI is not raised when number of corrected error
> > reaches preset threshold. After inspection, it is found that
> > MSR_IA32_MCI_CTL2 threshold field is not setup properly. This patch
> > fixed it.
> > 
> > Reported-by: Shaohui Zheng <shaohui.zheng@...el.com>
> > Signed-off-by: Huang Ying <ying.huang@...el.com>
> > Acked-by: Andi Kleen <ak@...ux.intel.com>
> > ---
> >  arch/x86/include/asm/mce.h             |    3 +++
> >  arch/x86/kernel/cpu/mcheck/mce_intel.c |    1 +
> >  2 files changed, 4 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> > index 6c3fdd6..355f298 100644
> > --- a/arch/x86/include/asm/mce.h
> > +++ b/arch/x86/include/asm/mce.h
> > @@ -38,6 +38,9 @@
> >  #define MCM_ADDR_MEM	 3	/* memory address */
> >  #define MCM_ADDR_GENERIC 7	/* generic */
> >  
> > +/* CTL2 register defines */
> > +#define MCI_CTL2_THRESHOLD_MASK	0x7fff
> > +
> >  #define MCJ_CTX_MASK		3
> >  #define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
> >  #define MCJ_CTX_RANDOM		0    /* inject context: random */
> > diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> > index d15df6e..ffe730d 100644
> > --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
> > +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> > @@ -101,6 +101,7 @@ static void cmci_discover(int banks, int boot)
> >  			continue;
> >  		}
> >  
> > +		val &= ~MCI_CTL2_THRESHOLD_MASK;
> >  		val |= CMCI_EN | CMCI_THRESHOLD;
> >  		wrmsrl(MSR_IA32_MCx_CTL2(i), val);
> >  		rdmsrl(MSR_IA32_MCx_CTL2(i), val);
> 
> Hum, it seems that the CTL2 of reported environment had
> be initialized to have more than CMCI_THRESHOLD(=1) by
> BIOS etc.  Could you explain more about your inspection?

In CTL2, threshold is initialized to 10 by BIOS.

> Maybe we could handle this environment if kernel supports
> APEI's firmware-first for corrected MCE and if this is in
> that case.

I still don't know much about the details of the interaction between
BIOS and OS here.

Best Regards,
Huang Ying

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