linux-kernel - Re: Microblaze

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Message-ID: <4BC57478.3080902@lumino.de>
Date:	Wed, 14 Apr 2010 09:53:28 +0200
From:	Michael Schnell <mschnell@...ino.de>
To:	monstr@...str.eu
CC:	microblaze-uclinux@...e.uq.edu.au,
	LKML <linux-kernel@...r.kernel.org>,
	John Williams <john.williams@...alogix.com>,
	John Linn <John.Linn@...inx.com>,
	Stefan Asserhall <stefan.asserhall@...inx.com>,
	Goran Bilski <goran@...inx.com>,
	"Steven J. Magnani" <steve@...idescorp.com>,
	Arnd Bergmann <arnd@...db.de>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	akpm@...ux-foundation.org, Ingo Molnar <mingo@...e.hu>,
	"Edgar E. Iglesias" <edgar.iglesias@...il.com>,
	Grant Likely <grant.likely@...retlab.ca>, sam@...nborg.org,
	stephenn@...inx.com, Karen Whelan <karen.whelan@...alogix.com>,
	Wendy Liang <wendy.liang@...alogix.com>
Subject: Re: Microblaze - The fist year

On 04/13/2010 03:27 PM, Michal Simek wrote:
>
> yes, futex is there. You can check it in
> arch/microblaze/include/asm/futex.h
Great ! I'll check how this is done.
>
>> Does Microblaze MMU Linux support SMP ?
>
> It is possible to connect several MicroBlazes but the problem is
> missing cache coherency modul. I hope that Xilinx will release any
> version which will support it.
> We haven't done any significant work to support it but it is expected
> solution which will happen.

Besides cache coherency, another problem might be doing FUTEX. here (I
suppose) SMP safe atomic user space operations are necessary. many
simple RISK (load/store-) CPUs don't provide these (new ARMs provide
"load-locked / store-conditional" on that behalf as an extension to the
load/store paradigm. I suppose these can be done in an SMP-safe way,
supposedly using the hardware that provides cache coherency).

-Michael
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