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Message-ID: <1271706291.7616.79.camel@groeck-laptop>
Date:	Mon, 19 Apr 2010 12:44:51 -0700
From:	Guenter Roeck <guenter.roeck@...csson.com>
To:	Wim Van Sebroeck <wim@...ana.be>
CC:	alan@...rguk.ukuu.org.uk,
	"andy.sharp@...tor.com" <andy.sharp@...tor.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
	"ralf@...ux-mips.org" <ralf@...ux-mips.org>
Subject: Re: [PATCH/RESEND] MIPS: Fix sibyte watchdog initialization

On Mon, 2010-04-19 at 15:19 -0400, Wim Van Sebroeck wrote:
> Hi Guenter,
> 
> > Watchdog configuration register and timer count register were interchanged,
> > causing wrong values to be written into both registers.
> > This caused watchdog triggered resets even if the watchdog was reset in time.
> > 
> > Signed-off-by: Guenter Roeck <guenter.roeck@...csson.com>
> 
> Signed-off-by: Wim Van Sebroeck <wim@...ana.be>
> 
> Just let me know when this can be added as a fix in the watchdog tree.
> 
The earlier the better from my perspective. 

Ralf may have had the mips tree in mind - might make sense to
synchronize with him.

Thanks,
Guenter


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