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Message-ID: <4BD2B9E9.5020607@redhat.com>
Date:	Sat, 24 Apr 2010 12:29:13 +0300
From:	Avi Kivity <avi@...hat.com>
To:	Zachary Amsden <zamsden@...hat.com>
CC:	Glauber Costa <glommer@...hat.com>,
	Jeremy Fitzhardinge <jeremy@...p.org>,
	Peter Zijlstra <peterz@...radead.org>, kvm@...r.kernel.org,
	linux-kernel@...r.kernel.org, Marcelo Tosatti <mtosatti@...hat.com>
Subject: Re: [PATCH 1/5] Add a global synchronization point for pvclock

On 04/24/2010 12:31 AM, Zachary Amsden wrote:
> On 04/22/2010 11:34 PM, Avi Kivity wrote:
>> On 04/23/2010 04:44 AM, Zachary Amsden wrote:
>>>    Or apply this patch.
>>> time-warp.patch
>>>
>>>
>>> diff -rup a/time-warp-test.c b/time-warp-test.c
>>> --- a/time-warp-test.c    2010-04-15 16:30:13.955981607 -1000
>>> +++ b/time-warp-test.c    2010-04-15 16:35:37.777982377 -1000
>>> @@ -91,7 +91,7 @@ static inline unsigned long long __rdtsc
>>>   {
>>>       DECLARE_ARGS(val, low, high);
>>>
>>> -    asm volatile("cpuid; rdtsc" : EAX_EDX_RET(val, low, high));
>>> +    asm volatile("cpuid; rdtsc" : EAX_EDX_RET(val, low, high) :: 
>>> "ebx", "ecx");
>>>
>>
>> Plus, replace cpuid by lfence/mfence.  cpuid will trap.
>>
>
> Does lfence / mfence actually serialize?  I thought there was some 
> great confusion about that not being the case on all AMD processors, 
> and possibly not at all on Intel.

They don't.

>
> A trap, however is a great way to serialize.
>
> I think, there is no serializing instruction which can be used from 
> userspace which does not trap, at least, I don't know one off the top 
> of my head.

iret.

-- 
Do not meddle in the internals of kernels, for they are subtle and quick to panic.

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