linux-kernel - Re: [PATCH] USB: isp1760: Soften DW3 X/transaction error bit handling

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 6 May 2010 15:53:54 -0400 (EDT)
From:	Alan Stern <stern@...land.harvard.edu>
To:	Anton Vorontsov <avorontsov@...sta.com>
cc:	Greg Kroah-Hartman <gregkh@...e.de>,
	Sebastian Siewior <bigeasy@...utronix.de>,
	Catalin Marinas <catalin.marinas@....com>,
	Bryan Wu <cooloney@...nel.org>, <linux-usb@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] USB: isp1760: Soften DW3 X/transaction error bit handling

On Thu, 6 May 2010, Anton Vorontsov wrote:

> It appears that the 'pehcd' driver checks the X bit only if the
> transaction is halted, otherwise the error is so far
> insignificant.
> 
> I didn't find where exactly ISP1760 spec mandates 'H && X'
> handling (maybe it's in the EHCI spec?),

Yes, it is described implicitly in the EHCI spec, section 4.10.3.
Transaction errors cause the status field to be updated to reflect the
type of error, but the transaction continues to be retried until the
Active bit is set to 0.  When the error counter reaches 0, the Halt bit
is set and the Active bit is cleared.

Alan Stern

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/