linux-kernel - Re: [PATCH] ad7877: keep dma rx buffers in seperate cache lines

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Date:	Sun, 9 May 2010 00:45:41 -0400
From:	Mike Frysinger <vapier.adi@...il.com>
To:	Johannes Weiner <jw@...ix.com>
Cc:	Oskar Schirmer <os@...ix.com>,
	Dmitry Torokhov <dmitry.torokhov@...il.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	linux-input@...r.kernel.org, linux-kernel@...r.kernel.org,
	Daniel Glöckner <dg@...ix.com>,
	Oliver Schneidewind <osw@...ix.com>
Subject: Re: [PATCH] ad7877: keep dma rx buffers in seperate cache lines

On Sat, May 8, 2010 at 18:32, Johannes Weiner wrote:
> On Fri, May 07, 2010 at 02:28:16PM -0400, Mike Frysinger wrote:
>> On Fri, May 7, 2010 at 06:15, Oskar Schirmer wrote:
>> > On Thu, May 06, 2010 at 14:46:04 -0400, Mike Frysinger wrote:
>> >> On Thu, May 6, 2010 at 06:37, Oskar Schirmer wrote:
>> >> >  struct ser_req {
>> >> > +       u16                     sample;
>> >> > +       char                    __padalign[L1_CACHE_BYTES - sizeof(u16)];
>> >> > +
>> >> >        u16                     reset;
>> >> >        u16                     ref_on;
>> >> >        u16                     command;
>> >> > -       u16                     sample;
>> >> >        struct spi_message      msg;
>> >> >        struct spi_transfer     xfer[6];
>> >> >  };
>> >>
>> >> are you sure this is necessary ?  ser_req is only ever used with
>> >> spi_sync() and it's allocated/released on the fly, so how could
>> >> anything be reading that memory between the start of the transmission
>> >> and the return to adi7877 ?
>> >
>> > msg is handed over to spi_sync, it contains the addresses
>> > which will be used to programme the DMA: the spi master
>> > transfer function will read these fields to start DMA.
>>
>> so the issue is coming from the SPI master drivers and not the AD7877 driver
>
> No, the issue is coming from ad7877 placing a transmission buffer
> into the same cache line with memory locations that are accessed outside
> the driver's scope.

you missed the point of my comment.  as i clearly explained in the
other structure, the AD7877 driver was causing the cache desync.  here
it is the SPI master that is implicitly causing it.  i'm not talking
about the AD7877 being correct wrt to the implicit SPI/DMA
requirements, just what code exactly is triggering the cache issues.

>  /*
>   * DMA (thus cache coherency maintainance) requires the
>   * transfer buffers to live in their own cache lines.
>   */
>   char         __padalign[...];
>
> ?  It might be obvious what the code does, but I agree with
> Mike that it might not be immediately apparent why it's needed.

comment looks fine once the spelling is fixed (maintenance).  thanks.
-mike
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