linux-kernel - Re: [RFC PATCH] Update the cachetlb.txt file WRT flush_dcache_pageand update_mmu

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Message-ID: <1273500010.10282.25.camel@e102109-lin.cambridge.arm.com>
Date:	Mon, 10 May 2010 15:00:10 +0100
From:	Catalin Marinas <catalin.marinas@....com>
To:	Matthew Wilcox <matthew@....cx>
Cc:	FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>,
	linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
	James.Bottomley@...senPartnership.com, benh@...nel.crashing.org,
	davem@...emloft.net, rmk@....linux.org.uk
Subject: Re: [RFC PATCH] Update the cachetlb.txt file WRT
 flush_dcache_pageand update_mmu_cache

On Mon, 2010-05-10 at 12:55 +0100, Matthew Wilcox wrote:
> On Mon, May 10, 2010 at 11:16:47AM +0100, Catalin Marinas wrote:
> > In most situations, just doing flushing in set_pte_at() would suffice
> > and flush_dcache_page() can be ignored. There are two situations where I
> > still see flush_dcache_page() useful:
> >
> >      1. SMP systems where the cache maintenance operations aren't
> >         automatically broadcast in hardware
> >      2. The kernel modifies a page cache page that is already mapped in
> >         user space
> >
> > (1) can be worked around on some architectures (though not sure about
> > all of them).
> >
> > Is (2) a valid scenario?
> 
> The kernel always calls kmap() / kunmap() around accesses to page cache
> pages (thanks to x86-32's ability to support 64GB).  There are three
> ways I know of that architectures use this:

I think this was mentioned in some past discussions. There are
situations where page cache pages aren't highmem pages and kmap/kunmap
isn't used:

http://thread.gmane.org/gmane.linux.ide/44847

But yes, that's a possible solution that ideally would need to be agreed
with the other architectures and write the recommendations in
cachetlb.txt. It may need, however, to update some of the drivers in
Linux.

It would also mean that some architectures need to implement the kmap
API even if they don't need it. That's David Miller's comment on
sparc64:

http://article.gmane.org/gmane.linux.ide/44872

> 1) No-ops.  These architectures don't have cache problems.
> 2) Flush the kernel's mapping in kunmap().  This can have bad consequences
> in SMP systems with threaded programs.
> 3) Select an address in kmap() that will alias to the user's address.

3rd point above would help with the D-cache aliasing. Does the I/D cache
coherency need to be handled differently? On PIPT Harvard architectures,
we don't actually have D-cache aliasing but we may end up flushing too
much in kunmap() just in case such page would be mapped in user space
with executable permission.

An alternative for a PIO API which would require fixing individual
drivers was proposed here:

http://thread.gmane.org/gmane.linux.kernel.cross-arch/5136

-- 
Catalin

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