linux-kernel - Re: [LKML] Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines

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Message-ID: <AANLkTin2Kz0rdecwMlu6DU5y4b_okl4gdXCcF2c1ZlT4@mail.gmail.com>
Date:	Wed, 12 May 2010 10:36:39 -0400
From:	Mike Frysinger <vapier.adi@...il.com>
To:	Marc Gauthier <marc@...silica.com>
Cc:	FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>,
	"npiggin@...e.de" <npiggin@...e.de>,
	"dmitry.torokhov@...il.com" <dmitry.torokhov@...il.com>,
	"jw@...ix.com" <jw@...ix.com>, "cl@...ux.com" <cl@...ux.com>,
	"penberg@...helsinki.fi" <penberg@...helsinki.fi>,
	"mpm@...enic.com" <mpm@...enic.com>,
	"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
	"os@...ix.com" <os@...ix.com>,
	"Michael.Hennerich@...log.com" <Michael.Hennerich@...log.com>,
	"linux-input@...r.kernel.org" <linux-input@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"dg@...ix.com" <dg@...ix.com>, "osw@...ix.com" <osw@...ix.com>,
	"rientjes@...gle.com" <rientjes@...gle.com>,
	"dbrownell@...rs.sourceforge.net" <dbrownell@...rs.sourceforge.net>,
	"grant.likely@...retlab.ca" <grant.likely@...retlab.ca>,
	"chris@...kel.net" <chris@...kel.net>,
	Piet Delaney <Piet.Delaney@...silica.com>
Subject: Re: [LKML] Re: [PATCH v3] ad7877: keep dma rx buffers in seperate 
	cache lines

On Wed, May 12, 2010 at 08:35, Marc Gauthier wrote:
> Mike Frysinger wrote:
>> On Tue, May 11, 2010 at 23:23, FUJITA Tomonori wrote:
>>> Seems that kmalloc is not cacheline aligned on some architectures but
>>> they works. Probably, we might be just lucky because in general they
>>> allocate larger buffers than 64 for DMA via kmalloc and the buffers
>>> are aligned on the size?
>>
>> i think the magic combo is:
>>  - DMA buffer is written to (receive)
> [...]
>>  - only on arches that need software cache coherency
>
> In particular, when the architecture port uses cache invalidates that
> throw away dirty lines.  They're equivalent to writing old data to a
> cache line, so an unrelated kmalloc allocation in the same cache line
> gets corrupted.

true; i was thinking of the Blackfin implementation that only has a
FLUSH+INV insn (i complain about the lack of a pure INV insn every now
and again)
-mike
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