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Message-ID: <20100514174153.GB10133@shareable.org> Date: Fri, 14 May 2010 18:41:53 +0100 From: Jamie Lokier <jamie@...reable.org> To: Russell King - ARM Linux <linux@....linux.org.uk> Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>, Saeed Bishara <saeed@...vell.com>, Nicolas Pitre <nico@...vell.com>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "James E.J. Bottomley" <jejb@...isc-linux.org>, FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>, "Shilimkar, Santosh" <santosh.shilimkar@...com>, Andrew Morton <akpm@...ux-foundation.org>, "linux-ext4@...r.kernel.org" <linux-ext4@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org> Subject: Re: Rampant ext3/4 corruption on 2.6.34-rc7 with VIVT ARM (Marvell 88f5182) Russell King - ARM Linux wrote: > On Thu, May 13, 2010 at 08:47:11AM +1000, Benjamin Herrenschmidt wrote: > > Now, in the case at hand, which is my ARM based NAS, I believe this > > is non cache-coherent and thus uses cache flush ops. I don't know ARM > > well enough but I would expect these to be implicit barriers. Russell ? > > Nico ? > > ARMv5 doesn't have a weak memory ordering model, and doesn't have any > memory barrier instructions. It does have buffered writes, doesn't it? Are they always flushed by the cache flush ops? -- Jamie -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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