linux-kernel - [tip:perf/core] perf, x86: P4 PMU -- do a real check for ESCR address being in hash

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Message-ID: <tip-623aab896ee1a532cb540bcf0d5ae8a88275afd5@git.kernel.org>
Date:	Wed, 19 May 2010 07:57:03 GMT
From:	tip-bot for Cyrill Gorcunov <gorcunov@...nvz.org>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
	gorcunov@...nvz.org, a.p.zijlstra@...llo.nl, fweisbec@...il.com,
	ming.m.lin@...el.com, tglx@...utronix.de, mingo@...e.hu
Subject: [tip:perf/core] perf, x86: P4 PMU -- do a real check for ESCR address being in hash

Commit-ID:  623aab896ee1a532cb540bcf0d5ae8a88275afd5
Gitweb:     http://git.kernel.org/tip/623aab896ee1a532cb540bcf0d5ae8a88275afd5
Author:     Cyrill Gorcunov <gorcunov@...nvz.org>
AuthorDate: Wed, 19 May 2010 01:19:17 +0400
Committer:  Ingo Molnar <mingo@...e.hu>
CommitDate: Wed, 19 May 2010 09:41:05 +0200

perf, x86: P4 PMU -- do a real check for ESCR address being in hash

To prevent from clashes in future code modifications
do a real check for ESCR address being in hash. At
moment the callers are known to pass sane values but
better to be on a safe side.

And comment fix.

Signed-off-by: Cyrill Gorcunov <gorcunov@...nvz.org>
CC: Lin Ming <ming.m.lin@...el.com>
CC: Peter Zijlstra <a.p.zijlstra@...llo.nl>
CC: Frederic Weisbecker <fweisbec@...il.com>
LKML-Reference: <20100518212439.004503600@...nvz.org>
Signed-off-by: Ingo Molnar <mingo@...e.hu>
---
 arch/x86/kernel/cpu/perf_event_p4.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 87e1803..5f8e36d 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -670,7 +670,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
 
 /*
  * ESCR address hashing is tricky, ESCRs are not sequential
- * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03e0) and
+ * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and
  * the metric between any ESCRs is laid in range [0xa0,0xe1]
  *
  * so we make ~70% filled hashtable
@@ -735,8 +735,9 @@ static int p4_get_escr_idx(unsigned int addr)
 {
 	unsigned int idx = P4_ESCR_MSR_IDX(addr);
 
-	if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE ||
-			!p4_escr_table[idx])) {
+	if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE	||
+			!p4_escr_table[idx]		||
+			p4_escr_table[idx] != addr)) {
 		WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);
 		return -1;
 	}
--
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