linux-kernel - tsc reliability for Intel Core 2 Duo "Conroe"

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <d1278473-1065-4607-98e0-67f2b985ec15@default>
Date:	Wed, 26 May 2010 10:41:43 -0700 (PDT)
From:	Dan Magenheimer <dan.magenheimer@...cle.com>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	linux-kernel@...r.kernel.org
Subject: tsc reliability for Intel Core 2 Duo "Conroe"

Looking through code following up on the separate TSC-related
thread, I noticed that my Intel Core 2 Duo "Conroe" box
is determined to have an unstable TSC, so falls back
to clocksource==hpet.

While a Conroe has X86_FEATURE_CONSTANT_TSC and not
X86_FEATURE_NONSTOP_TSC, a Conroe is only able to enter
C0 and C1 (unlike its sister Intel Core 2 Duo processor
"Merom" which can enter C0-C3).

I was under the impression (possibly from an earlier kernel
version?) that tsc_constant PLUS inability to enter deep-C
states would result in an acceptably stable TSC to use
as a clocksource (assuming it passes a TSC warp test).

So is this a bug?  Or is my impression incorrect?

See tsc_check_state() in drivers/acpi/processor_idle.c.
I can submit a patch, but wanted to check first.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/