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Message-ID: <20100528094115.30547.20855.stgit@warthog.procyon.org.uk>
Date: Fri, 28 May 2010 10:41:16 +0100
From: David Howells <dhowells@...hat.com>
To: torvalds@...l.org, akpm@...ux-foundation.org
Cc: linux-kernel@...r.kernel.org, David Howells <dhowells@...hat.com>,
FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>
Subject: [PATCH] FRV: ARCH_KMALLOC_MINALIGN was already defined
ARCH_KMALLOC_MINALIGN was already defined in asm/mem-layout.h and so shouldn't
have been added to asm/cache.h as well, but rather altered in place.
The commit that added it to asm/cache.h was:
commit 69dcf3db03626c4f18de624e8632454ea12ff260
Author: FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>
Date: Mon May 24 14:32:54 2010 -0700
frv: set ARCH_KMALLOC_MINALIGN
Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is
DMA-safe: the buffer doesn't share a cache with the others.
Signed-off-by: David Howells <dhowells@...hat.com>
cc: FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>
---
arch/frv/include/asm/cache.h | 2 --
arch/frv/include/asm/mem-layout.h | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/frv/include/asm/cache.h b/arch/frv/include/asm/cache.h
index 7dc0f0f..2797163 100644
--- a/arch/frv/include/asm/cache.h
+++ b/arch/frv/include/asm/cache.h
@@ -17,8 +17,6 @@
#define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT)
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
-
#define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h
index 2947764..ccae981 100644
--- a/arch/frv/include/asm/mem-layout.h
+++ b/arch/frv/include/asm/mem-layout.h
@@ -35,8 +35,8 @@
* the slab must be aligned such that load- and store-double instructions don't
* fault if used
*/
-#define ARCH_KMALLOC_MINALIGN 8
-#define ARCH_SLAB_MINALIGN 8
+#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
/*****************************************************************************/
/*
--
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