linux-kernel - Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root bus

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Date:	Mon, 14 Jun 2010 11:39:54 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Bjorn Helgaas <bjorn.helgaas@...com>
CC:	Yinghai Lu <yinghai.lu@...cle.com>,
	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>,
	Graham Ramsey <ramsey.graham@...world.com>,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	Robert Richter <robert.richter@....com>,
	Harald Welte <HaraldWelte@...tech.com>,
	Joseph Chan <JosephChan@....com.tw>,
	Jiri Slaby <jslaby@...e.cz>,
	Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Dominik Brodowski <linux@...inikbrodowski.net>
Subject: Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root
 bus

On 06/14/2010 11:34 AM, Bjorn Helgaas wrote:
> 
> I made the point there that an HT chain may contain multiple HT/PCI
> host bridges, but you are stuck on the idea that "one HT chain == one
> PCI root bus."
> 
> I have not found the "one PCI host bridge per HT chain" requirement
> in the HT spec (if you find it, please point me to it).
> 
> If an HT chain may contain multiple HT/PCI host bridges, then it's
> obvious that the HT host bridge registers read by amd_bus.c don't
> contain enough information to correctly assign address space to the
> PCI root buses.
> 

A HT-to-PCI bridge appears as a PCI-to-PCI bridge (i.e. a Header Type 1
device), not as a host bridge (a Header Type 0 device).

That is at least the software model as defined.

	-hpa
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