linux-kernel - Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root bus

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Mon, 14 Jun 2010 13:43:32 -0600
From:	Bjorn Helgaas <bjorn.helgaas@...com>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	Yinghai Lu <yinghai.lu@...cle.com>,
	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>,
	Graham Ramsey <ramsey.graham@...world.com>,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	Robert Richter <robert.richter@....com>,
	Harald Welte <HaraldWelte@...tech.com>,
	Joseph Chan <JosephChan@....com.tw>,
	Jiri Slaby <jslaby@...e.cz>,
	Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Dominik Brodowski <linux@...inikbrodowski.net>
Subject: Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root bus

On Monday, June 14, 2010 12:39:54 pm H. Peter Anvin wrote:
> On 06/14/2010 11:34 AM, Bjorn Helgaas wrote:
> > 
> > I made the point there that an HT chain may contain multiple HT/PCI
> > host bridges, but you are stuck on the idea that "one HT chain == one
> > PCI root bus."
> > 
> > I have not found the "one PCI host bridge per HT chain" requirement
> > in the HT spec (if you find it, please point me to it).
> > 
> > If an HT chain may contain multiple HT/PCI host bridges, then it's
> > obvious that the HT host bridge registers read by amd_bus.c don't
> > contain enough information to correctly assign address space to the
> > PCI root buses.
> 
> A HT-to-PCI bridge appears as a PCI-to-PCI bridge (i.e. a Header Type 1
> device), not as a host bridge (a Header Type 0 device).
> 
> That is at least the software model as defined.

Certainly that's what the HT I/O Link spec (v3.10, sec 7.4) suggests,
and I think I saw hints that AMD chipsets do that.  I can't tell from
the HT I/O spec whether it would be an actual defect to use host bridges
instead of PCI-to-PCI bridges, and I can imagine why one might want to
leave an existing PCI host bridge design alone and merely glue on an
HT interface, rather than redesign the bridge register set.

In any case, the VIA chipset in Graham's machine does not have a
PCI-to-PCI bridge leading to bus 80 (see
https://bugzilla.kernel.org/show_bug.cgi?id=16007#c14).
However, ACPI *does* report a PCI host bridge leading to bus 80,
and the apertures it reports seem to be correct (see
https://bugzilla.kernel.org/show_bug.cgi?id=16007#c6).

Bjorn
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/