linux-kernel - Re: [PATCH 15/17] Fix AMD C1 TSC desynchronization

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Message-ID: <20100615144601.GD15264@amd.com>
Date:	Tue, 15 Jun 2010 16:46:01 +0200
From:	"Roedel, Joerg" <Joerg.Roedel@....com>
To:	Zachary Amsden <zamsden@...hat.com>
CC:	Avi Kivity <avi@...hat.com>,
	"mtosatti@...hat.com" <mtosatti@...hat.com>,
	"glommer@...hat.com" <glommer@...hat.com>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 15/17] Fix AMD C1 TSC desynchronization

On Tue, Jun 15, 2010 at 05:21:11AM -0400, Zachary Amsden wrote:
> On 06/14/2010 10:47 PM, Avi Kivity wrote:
> > On 06/15/2010 10:34 AM, Zachary Amsden wrote:
> >> +    /*
> >> +     * AMD processors can de-synchronize TSC on halt in C1 state, 
> >> because
> >> +     * processors in lower P state will have TSC scaled properly during
> >> +     * normal operation, but will have TSC scaled improperly while
> >> +     * servicing cache probes.  Because there is no way to determine 
> >> how
> >> +     * TSC was adjusted during cache probes, there are two solutions:
> >> +     * resynchronize after halt, or disable C1-clock ramping.
> >> +     *
> >> +     * We implemenent solution 2.
> >> +     */
> >> +#ifdef CONFIG_K8_NB
> >> +    if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD&&
> >> +        boot_cpu_data.x86 == 0x0f&&
> >> +        !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
> >> +        struct pci_dev *nb;
> >> +        int i;
> >> +        cache_k8_northbridges();
> >> +        for (i = 0; i<  num_k8_northbridges; i++) {
> >> +            u8 byte;
> >> +            nb = k8_northbridges[i];
> >> +            pci_read_config_byte(nb, 0x87,&byte);
> >> +            if (byte&  1) {
> >> +                printk(KERN_INFO "%s: AMD C1 clock ramping detected, 
> >> performing workaround\n", __func__);
> >> +                disabled_c1_ramp = byte;
> >> +                pci_write_config_byte(nb, 0x87, byte&  0xFC);
> >> +
> >> +            }
> >> +        }
> >> +    }
> >> +#endif

This is dangerous to do as a general thing on all Fam0fh based AMD
systems, especially mobile ones and especially since some distributions
load the kvm modules at boot per default.
The BIOS should set meaningful default values for PMM7 and the
recommended default value for servers already set this bit to zero.

> I agree it is complete hackery.  I do not recommend this patch for 
> upstream inclusion unless it is proposed also by someone more familiar 
> with the hardware.

I will check again with some other people inside AMD, but my current
suggestion would be to not provide kvm-clock to the guest if running on
an AMD Fam0fh processor in an SMP environemnt with PMM7.0 set. This also
sucks in its own way but is safer than just disable clock ramping on all
affected processors.

	Joerg


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