linux-kernel - [PATCH RESEND] (revised) Calgary: increase max PHB number

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Date:	Mon, 21 Jun 2010 14:41:50 -0400
From:	Corinna Schultz <cschultz@...ux.vnet.ibm.com>
To:	mingo@...e.hu
Cc:	linux-kernel@...r.kernel.org, akpm@...ux-foundation.org,
	djwong@...ibm.com, coschult@...ibm.com
Subject: [PATCH RESEND] (revised) Calgary: increase max PHB number

There was a small difference in 35-rc3 that prevented this patch from  
applying, so I regenerated it.

===============================

Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so  
bump the
limits up and provide an explanation of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong@...ibm.com>
Acked-by: Muli Ben-Yehuda <muli@...ibm.com>

--- a/arch/x86/kernel/pci_calgary_64.c     2010-06-21 10:57:15.000000000 -0700
+++ b/arch/x86/kernel/pci_calgary_64.c    2010-06-21 11:01:56.000000000 -0700
@@ -103,10 +103,15 @@
  #define PMR_SOFTSTOPFAULT      0x40000000
  #define PMR_HARDSTOP           0x20000000

-#define MAX_NUM_OF_PHBS                8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS                8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM                (MAX_NUM_OF_PHBS *  
MAX_NUM_CHASSIS * 2)
+/*
+ * The maximum PHB bus number.
+ * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
+ * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
+ * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
+ */
+#define MAX_PHB_BUS_NUM       384
+
  #define PHBS_PER_CALGARY       4

  /* register offsets in Calgary's internal register space */





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