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Date:	Fri, 25 Jun 2010 15:34:28 +0200
From:	Christoph Mair <christoph.mair@...il.com>
To:	"Datta, Shubhrajyoti" <shubhrajyoti@...com>
Cc:	Jonathan Cameron <kernel@...23.retrosnub.co.uk>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [PATCH] BMP085 : Change the macro to swap

On Fri, Jun 25, 2010 at 3:00 PM, Datta, Shubhrajyoti
<shubhrajyoti@...com> wrote:
>
>
>> -----Original Message-----
>> From: J.I. Cameron [mailto:jic23@...mes.cam.ac.uk] On Behalf Of Jonathan
>> Cameron
>> Sent: Thursday, June 24, 2010 6:23 PM
>> To: Datta, Shubhrajyoti
>> Cc: linux-kernel@...r.kernel.org; Christoph Mair; Andrew Morton
>> Subject: Re: [PATCH] BMP085 : Change the macro to swap
>>
>> On 06/24/10 13:41, Datta, Shubhrajyoti wrote:
>> >
>> > Changing the macro to swap the bytes as the reason that the first byte
>> is the MSB and the next is LSB.
>> Are you sure on this one?
>
> The datasheet says the  E2PROM has the bytes as described in the comment below
> *
> * BMP085 Reg Addr
> * parameter     |       MSB     |       LSB
> * AC1           |       0xAA    |       0xAB
> ...
>
> AA has MSB and AB has lsb so it has to be swapped. My idea is that it does not depend on the endianness of the CPU running the code. So I think that swap should happen unconditionally. The I2C reads a string of bytes and the first byte from AA and next from AB and hence an unconditional swap maybe needed.
>
> Am I missing something.
The data is read bytewise and stored in memory starting with
MSB-LSM-MSB-LSB-... If you have a big endian CPU, it expects a 16 Bit
word to be stored in exactly this format. A little endian CPU expects
the LSB to be stored at the lower memory address: LSB-MSB.
Therefore the bytes have to be swapped only for little-endian cpus.

Best regards,
  Christoph
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