linux-kernel - Re: [PATCH -next] tile: remove homegrown L1_CACHE

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Message-ID: <4C29F0D1.7030704@tilera.com>
Date:	Tue, 29 Jun 2010 09:10:41 -0400
From:	Chris Metcalf <cmetcalf@...era.com>
To:	FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>
CC:	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH -next] tile: remove homegrown L1_CACHE_ALIGN macro

This looks fine, thanks.

Acked-by: Chris Metcalf <cmetcalf@...era.com>

On 6/29/2010 3:32 AM, FUJITA Tomonori wrote:
> Let's use the standard L1_CACHE_ALIGN macro instead.
>
> Signed-off-by: FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>
> ---
>  arch/tile/include/asm/cache.h |    1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
> index c2b7dcf..ee59714 100644
> --- a/arch/tile/include/asm/cache.h
> +++ b/arch/tile/include/asm/cache.h
> @@ -20,7 +20,6 @@
>  /* bytes per L1 data cache line */
>  #define L1_CACHE_SHIFT		CHIP_L1D_LOG_LINE_SIZE()
>  #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
> -#define L1_CACHE_ALIGN(x)	(((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
>  
>  /* bytes per L1 instruction cache line */
>  #define L1I_CACHE_SHIFT		CHIP_L1I_LOG_LINE_SIZE()
>   

-- 
Chris Metcalf, Tilera Corp.
http://www.tilera.com

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