linux-kernel - Re: [PATCH] x86, Calgary: Increase max PHB number

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Message-ID: <4C2BCDC6.1010004@zytor.com>
Date:	Wed, 30 Jun 2010 16:05:42 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	djwong@...ibm.com
CC:	Andrew Morton <akpm@...ux-foundation.org>, mingo@...hat.com,
	linux-kernel@...r.kernel.org, muli@...ibm.com,
	cschultz@...ux.vnet.ibm.com, stable@...nel.org, tglx@...utronix.de,
	mingo@...e.hu, linux-tip-commits@...r.kernel.org
Subject: Re: [PATCH] x86, Calgary: Increase max PHB number

On 06/30/2010 02:49 PM, Darrick J. Wong wrote:
> Newer systems (x3950M2) can have 48 PHBs per chassis and 4 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.  Since
> we can't have more than 256 PCI buses in these systems, we don't need the array
> check.

The 384-entry patch is already upstream.  Can you send a patch relative
to current -linus?

	-hpa

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