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Message-ID: <4C3DFA88.5020007@goop.org>
Date: Wed, 14 Jul 2010 10:57:28 -0700
From: Jeremy Fitzhardinge <jeremy@...p.org>
To: "H. Peter Anvin" <hpa@...or.com>
CC: Linus Torvalds <torvalds@...ux-foundation.org>,
Peter Palfrader <peter@...frader.org>,
Avi Kivity <avi@...hat.com>, Greg KH <gregkh@...e.de>,
linux-kernel@...r.kernel.org, stable@...nel.org,
stable-review@...nel.org, akpm@...ux-foundation.org,
alan@...rguk.ukuu.org.uk, Glauber Costa <glommer@...hat.com>,
Zachary Amsden <zamsden@...hat.com>,
Marcelo Tosatti <mtosatti@...hat.com>
Subject: Re: [patch 134/149] x86, paravirt: Add a global synchronization point
for pvclock
On 07/14/2010 10:45 AM, H. Peter Anvin wrote:
> On 07/14/2010 10:34 AM, Jeremy Fitzhardinge wrote:
>
>> On 07/14/2010 10:30 AM, H. Peter Anvin wrote:
>>
>>> If gcc ever starts reordering volatile operations, including "asm
>>> volatile", the kernel will break, and will be unfixable. Just about
>>> every single driver will break. All over the kernel we're explicitly or
>>> implicitly making the assumption that volatile operations are strictly
>>> ordered by the compiler with respect to each other.
>>>
>> Can you give an example? All the cases I've seen rely on the ordering
>> properties of "memory" clobbers, which is sound. (And volatile
>> variables are a completely unrelated issue, of course.)
>>
>>
> I/O ports, for example.
>
Yes, it looks like they should have memory barriers if we want them to
be ordered with respect to normal writes; afaict "asm volatile" has
never had strict ordering wrt memory ops.
Anything else?
J
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