linux-kernel - Re: [PATCH + an old question] firewire: ohci: use memory barriers to order descriptor updates

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Date:	Wed, 28 Jul 2010 09:28:06 +0200
From:	Clemens Ladisch <clemens@...isch.de>
To:	Stefan Richter <stefanr@...6.in-berlin.de>
CC:	linux-kernel@...r.kernel.org, linux1394-devel@...ts.sourceforge.net
Subject: Re: [PATCH + an old question] firewire: ohci: use memory barriers
 to order descriptor updates

Stefan Richter wrote:
> We need:
> 2. a write memory barrier between branch_address update and wake-up of
>    the DMA unit by MMIO register write.
> 
> Barrier 2 is implicit in writel() on most machines --- or at least I
> think it is.  See this from arch/x86/include/asm/io.h:
> 
>     #define build_mmio_write(name, size, type, reg, barrier) \
>     static inline void name(type val, volatile void __iomem *addr) \
>     { asm volatile("mov" size " %0,%1": :reg (val), \
>     "m" (*(volatile type __force *)addr) barrier); }
> 
>     build_mmio_write(writel, "l", unsigned int, "r", :"memory")
> 
> Does this order the mmio write relative to previous memory writes?

This asm barrier prevents the compiler from reordering.

The main purpose of writel() and friends is to access the address space
where memory-mapped I/O ranges reside; there are architectures where the
normal memory access commands cannot be used.  This does not necessarily
imply anything about reordering semantics.

However, PCI address ranges are marked by the device's config registers
as either cacheable or not, and the kernel heeds this when mapping these
ranges.  Registers are, of course, marked as uncacheable.


Regards,
Clemens
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