linux-kernel - RE: [PATCH 2/9] RapidIO, powerpc/85xx: modify RIO port-write interrupt handler

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Message-ID: <0CE8B6BE3C4AD74AB97D9D29BD24E552011D5F94@CORPEXCH1.na.ads.idt.com>
Date:	Mon, 16 Aug 2010 08:27:34 -0700
From:	"Bounine, Alexandre" <Alexandre.Bounine@....com>
To:	"Micha Nelissen" <micha@...i.hopto.org>
Cc:	<akpm@...ux-foundation.org>, <linux-kernel@...r.kernel.org>,
	<linuxppc-dev@...abs.org>,
	"Bounine, Alexandre" <Alexandre.Bounine@....com>
Subject: RE: [PATCH 2/9] RapidIO,  powerpc/85xx: modify RIO port-write interrupt handler

Micha Nelissen wrote:
> 
> Alexandre Bounine wrote:
> > - Rearranged RIO port-write interrupt handling to perform message
buffering
> > as soon as possible.
> 
> I don't understand this comment: you still schedule work to read the
> port-write queue; so how is this message buffering performed as soon
as
> possible?


Compared to the original code, I rearranged order of checking interrupt
status bits to check the queue status first. The 85xx PW controller is
capable to receive and keep only one PW message. Therefore, I copy it
into the driver's FIFO and re-enable HW Rx queue (it is called queue but
can accept only one entry) ASAP. I have a test setup that is capable
generate multiple PW messages and see many messages discarded by PW
controller
because of this single-entry HW queue.
 
> 
> > - Modified to disable port-write controller when clearing
Transaction Error (TE)
> > bit.
> >  	/* Schedule deferred processing if PW was received */
> > -	if (ipwsr & RIO_IPWSR_QFI) {
> > +	if ((ipwmr & RIO_IPWMR_QFIE) && (ipwsr & RIO_IPWSR_QFI)) {
> 
> Why check the QFIE bit also?

Oops! Leftover from some testing. Will clean it up.

> 
> > +pw_done:
> > +	if (epwisr & 0x80000000) {
> 
> Magic value.


Agree. Will correct.


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