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Message-ID: <87y6bxqvfb.fsf@pollan.anholt.net>
Date:	Mon, 23 Aug 2010 07:02:16 -0700
From:	Eric Anholt <eric@...olt.net>
To:	Zhenyu Wang <zhenyuw@...ux.intel.com>, Takashi Iwai <tiwai@...e.de>
Cc:	David Airlie <airlied@...ux.ie>, dri-devel@...ts.freedesktop.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] agp/intel: Fix dma mask for Sandybridge

On Mon, 23 Aug 2010 14:48:54 +0800, Zhenyu Wang <zhenyuw@...ux.intel.com> wrote:
> On 2010.08.23 08:31:42 +0200, Takashi Iwai wrote:
> > > bit 31			 bit 11			 bit 4			bit 0
> > >    |<-physical addr 31:12->|<-physical addr 39:32->|<-cache ctl 3:1->|valid|
> > 
> > Then I really don't understand why it works.
> > You shift 28bit and mask with 0xff.  Obviously it overwrite bits 0:3
> > with original 28:31 bits.  Masking 0xff0 fixes the issue.
> > 
> 
> ah, sorry, my stupid. Thanks for catching this!
> 
> Subject: [PATCH] agp/intel: fix physical address mask bits for sandybridge
> 
> It should shift bit 39-32 into pte's bit 11-4.

Applied.  Thanks!

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