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Date: Mon, 6 Sep 2010 21:03:50 -0700 From: Kevin Cernekee <cernekee@...il.com> To: Ralf Baechle <ralf@...ux-mips.org> Cc: <linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org> Subject: [PATCH 4/5] MIPS: Honor L2 bypass bit If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and therefore Linux should not attempt to use it. Signed-off-by: Kevin Cernekee <cernekee@...il.com> --- arch/mips/mm/sc-mips.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 5ab5fa8..d072b25 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void) return 0; config2 = read_c0_config2(); + + /* bypass bit */ + if (config2 & (1 << 12)) + return 0; + tmp = (config2 >> 4) & 0x0f; if (0 < tmp && tmp <= 7) c->scache.linesz = 2 << tmp; -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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