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Message-ID: <677002.54522.qm@web180309.mail.gq1.yahoo.com>
Date: Mon, 6 Sep 2010 17:41:42 -0700 (PDT)
From: David Brownell <david-b@...bell.net>
To: Florian Fainelli <florian@...nwrt.org>
Cc: Willy Tarreau <w@....eu>, linux-kernel@...r.kernel.org,
akpm@...ux-foundation.org, Samuel Ortiz <sameo@...ux.intel.com>,
Miguel Gaio <miguel.gaio@...xo.com>,
Juhos Gabor <juhosg@...nwrt.org>
Subject: Re: [PATCH v4] GPIO: add support for 74x164 serial-in/parallel-out 8-bit shift register
--- On Wed, 9/1/10, Florian Fainelli <florian@...nwrt.org> wrote:
>
> Changes since v3:
> - support daisy-chaining of 74x164 up to 32 gpios
cool, a new feature!
I kind of dislike doing this after having
offereed feedback that you accepted, but I'm going
to NAK this driver for mainline.
The reasons are associated with a point I made in
my last feedback. The chip interface is SPI (but
it's not called that in the data sheets, true).
This driver is two things:
- maybe 85% looks like spi-over-gpio, cloning what
the spi-gpio.c driver does (a three-wire SPI mode,
using the NO_RX option, vs normal four-wire).
The rest is a small 74x164 driver.
So if there are spare GPIOs *this* driver can be
used, but not if there's just a spare SPI select.
If this were re-packaged as a small SPI protocol
driver and a small SPI-over-GPIO instance both of
the two components would be more reusable...
Your current hardware can handle the SPI-over-GPIO
approach, obviously.
I'd ack a small 74x164 SPI protocol driver, which is
what I expected when I saw the first post. But a
conglomerate driver -- no. Sorry.
- Dave
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