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Message-ID: <083DF309106F364B939360100EC290F80AD49D5230@eu1rdcrdc1wx030.exi.nxp.com>
Date: Mon, 13 Sep 2010 18:51:57 +0200
From: Kevin Wells <kevin.wells@....com>
To: Kevin Wells <wellsk40@...il.com>,
"sameo@...ux.intel.com" <sameo@...ux.intel.com>,
"rabin.vincent@...ricsson.com" <rabin.vincent@...ricsson.com>,
"linus.walleij@...ricsson.com" <linus.walleij@...ricsson.com>,
"srinidhi.kasagar@...ricsson.com" <srinidhi.kasagar@...ricsson.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux@....linux.org.uk" <linux@....linux.org.uk>,
"u.kleine-koenig@...gutronix.de" <u.kleine-koenig@...gutronix.de>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"tj@...nel.org" <tj@...nel.org>,
"grant.likely@...retlab.ca" <grant.likely@...retlab.ca>,
"spi-devel-general@...ts.sourceforge.net"
<spi-devel-general@...ts.sourceforge.net>
CC: "quentinyang05@...il.com" <quentinyang05@...il.com>,
"Lukasz.Baj@...to.com" <Lukasz.Baj@...to.com>
Subject: RE: resend: [PATCH] amba_pl022: Setup SPI configuration based on
spi->mode
> + if (spi->mode & SPI_CPOL)
> + tmp = SSP_CLK_POL_IDLE_HIGH;
> + else
> + tmp = SSP_CLK_POL_IDLE_LOW;
> + SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
> +
> + if (spi->mode & SPI_CPHA)
> + tmp = SSP_CLK_SECOND_EDGE;
> + else
> + tmp = SSP_CLK_FIRST_EDGE;
> + SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 6);
SSP_CR0_MASK_SPH (SPHA) should use bit 7, not bit 6.
Should be:
SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
> +
> SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR,
> 8);
> /* Loopback is available on all versions except PL023 */
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