linux-kernel - Re: [PATCH RFC] x86: hpet: Avoid the readback penalty

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Message-Id: <1284558206l.9382l.2l@i-dmzi_al.realan.de>
Date:	Wed, 15 Sep 2010 15:43:26 +0200
From:	Anders Larsen <al@...rsen.net>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	LKML <linux-kernel@...r.kernel.org>, Ingo Molnar <mingo@...e.hu>,
	"H. Peter Anvin" <hpa@...or.com>, Nix <nix@...eri.org.uk>,
	Artur Skawina <art.08.09@...il.com>,
	Damien Wyart <damien.wyart@...e.fr>,
	John Drescher <drescherjm@...il.com>,
	Venkatesh Pallipadi <venki@...gle.com>,
	Arjan van de Ven <arjan@...ux.intel.com>,
	Andreas Herrmann <andreas.herrmann3@....com>,
	Borislav Petkov <borislav.petkov@....com>,
	Suresh Siddha <suresh.b.siddha@...el.com>
Subject: Re: [PATCH RFC] x86: hpet: Avoid the readback penalty

On 2010-09-15 15:11:57, Thomas Gleixner wrote:
> -	 * We need to read back the CMP register on certain HPET
> -	 * implementations (ATI chipsets) which seem to delay the
> -	 * transfer of the compare register into the internal compare
> -	 * logic. With small deltas this might actually be too late as
> -	 * the counter could already be higher than the compare value
> -	 * at that point and we would wait for the next hpet interrupt
> -	 * forever. We found out that reading the CMP register back
> -	 * forces the transfer so we can rely on the comparison with
> -	 * the counter register below. If the read back from the
> -	 * compare register does not match the value we programmed
> -	 * then we might have a real hardware problem. We can not do
> -	 * much about it here, but at least alert the user/admin with
> -	 * a prominent warning.
> -	 *
> -	 * An erratum on some chipsets (ICH9,..), results in
> -	 * comparator read immediately following a write returning old
> -	 * value. Workaround for this is to read this value second
> -	 * time, when first read returns old value.
> -	 *
> -	 * In fact the write to the comparator register is delayed up
> -	 * to two HPET cycles so the workaround we tried to restrict
> -	 * the readback to those known to be borked ATI chipsets
> -	 * failed miserably. So we give up on optimizations forever
> -	 * and penalize all HPET incarnations unconditionally.
> +	 * HPETs are a complete disaster. The compare register is
> +	 * based on a equal comparison and does provide a less than or

s/does provide/does not provide/

> +	 * equal functionality (which would require to take the
> +	 * wraparound into account) and it does not provide a simple
> +	 * count down event mode. Further the write to the comparator
> +	 * register is delayed internaly up to two HPET clock cycles

s/internaly/internally/

> +	 * in certain chipsets (ATI, ICH9,10). We worked around that
> +	 * by reading back the compare register, but that required
> +	 * another workaround for ICH9,10 chips where the first
> +	 * readout after write can return the old stale value. We
> +	 * already have a minimum delta of 5us enforced, but a NMI or
> +	 * SMI hitting between the counter readout and the comparator
> +	 * write can move us behind that point easily. Now instead of
> +	 * reading the compare register back several times, we make
> +	 * the ETIME decision based on the following: Return ETIME if
> +	 * the counter value after the write is less than 8 HPET
> +	 * cycles away from the event or if the counter is already
> +	 * ahead of the event.

Cheers
Anders


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