[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20100915172805.GR13563@erda.amd.com>
Date: Wed, 15 Sep 2010 19:28:05 +0200
From: Robert Richter <robert.richter@....com>
To: Cyrill Gorcunov <gorcunov@...il.com>
CC: Stephane Eranian <eranian@...gle.com>, Ingo Molnar <mingo@...e.hu>,
Peter Zijlstra <peterz@...radead.org>,
Don Zickus <dzickus@...hat.com>,
"fweisbec@...il.com" <fweisbec@...il.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"ying.huang@...el.com" <ying.huang@...el.com>,
"ming.m.lin@...el.com" <ming.m.lin@...el.com>,
"yinghai@...nel.org" <yinghai@...nel.org>,
"andi@...stfloor.org" <andi@...stfloor.org>
Subject: Re: [PATCH] perf, x86: catch spurious interrupts after disabling
counters
On 15.09.10 13:02:22, Cyrill Gorcunov wrote:
> > what's for sure, is that you can have an interrupt in flight by the time
> > you disable.
> >
>
> I fear you can x86_pmu_stop()
>
> if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
>
> ---> active_mask will be cleared here for sure
> ---> but counter still ticks, say nmi happens active_mask
> ---> is cleared, but NMI can still happen and gets buffered
> ---> before you disable counter in real
>
> x86_pmu.disable(event);
> cpuc->events[hwc->idx] = NULL;
> WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
> hwc->state |= PERF_HES_STOPPED;
> }
>
> No?
I tried reordering this too, but it didn't fix it.
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists