linux-kernel - Re: [PATCH 2/2] x86, CPUID: Correct operator precedence when generating mask

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Message-ID: <20100921120027.GB15756@aftab>
Date:	Tue, 21 Sep 2010 14:00:27 +0200
From:	Borislav Petkov <bp@...64.org>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	Ingo Molnar <mingo@...e.hu>, Thomas Gleixner <tglx@...utronix.de>,
	LKML <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH 2/2] x86, CPUID: Correct operator precedence when
 generating mask

From: "H. Peter Anvin" <hpa@...or.com>
Date: Mon, Sep 20, 2010 at 11:11:43AM -0400

> Since this is a non-manifest bug there really doesn't seem to be any
> reason to bother stable with it.

--
From: Borislav Petkov <borislav.petkov@....com>
Date: Tue Sep 21 13:56:59 CEST 2010
Subject: [PATCH] x86, CPUID: Correct operator precedence when generating mask

NEED_<cpufeature> masks used in the CPU feature testing macros are
cutoff at the last 5 bits to prevent overflow since the cpu feature
words are 32-bit-wide bitfields. Fix this for the PSE and PGE masks too.

This wasn't a real problem since the PSE and PGE bits are nicely < 31.

Signed-off-by: Borislav Petkov <borislav.petkov@....com>
---
 arch/x86/include/asm/required-features.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index 6c7fc25..0df924d 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -53,8 +53,8 @@
 #define NEED_PSE	0
 #define NEED_PGE	0
 #else
-#define NEED_PSE	(1<<(X86_FEATURE_PSE) & 31)
-#define NEED_PGE	(1<<(X86_FEATURE_PGE) & 31)
+#define NEED_PSE	(1<<(X86_FEATURE_PSE & 31))
+#define NEED_PGE	(1<<(X86_FEATURE_PGE & 31))
 #endif
 #define NEED_MSR	(1<<(X86_FEATURE_MSR & 31))
 #define NEED_FXSR	(1<<(X86_FEATURE_FXSR & 31))
-- 
1.7.1


-- 
Regards/Gruss,
Boris.

Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
General Managers: Alberto Bozzo, Andrew Bowd
Registration: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632
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