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Message-Id: <1285281496-24696-4-git-send-email-ddaney@caviumnetworks.com>
Date: Thu, 23 Sep 2010 15:38:10 -0700
From: David Daney <ddaney@...iumnetworks.com>
To: linux-mips@...ux-mips.org, ralf@...ux-mips.org,
linux-kernel@...r.kernel.org
Cc: David Daney <ddaney@...iumnetworks.com>
Subject: [PATCH 3/9] MIPS: Octeon: Adjust top of DMA32 zone.
On OCTEON, we reserve the last 256MB of 32-bit PCI address space,
mapping the RAM in this region at a high DMA address. This makes
memory in this region unavailable for 32-bit DMA.
Signed-off-by: David Daney <ddaney@...iumnetworks.com>
---
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index b952fc7..c84ed74 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -81,4 +81,10 @@ static inline int octeon_has_saa(void)
return id >= 0x000d0300;
}
+/*
+ * The last 256MB are reserved for device to device mappings and the
+ * BAR1 hole.
+ */
+#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
+
#endif
--
1.7.2.2
--
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