linux-kernel - Re: alpha: potential race around hae_cache in RESTORE

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Date:	Mon, 27 Sep 2010 20:01:09 +0100
From:	Al Viro <viro@...IV.linux.org.uk>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	Ivan Kokshaysky <ink@...assic.park.msu.ru>, rth@...ddle.net,
	linux-kernel@...r.kernel.org, Matt Turner <mattst88@...il.com>
Subject: Re: alpha: potential race around hae_cache in RESTORE_ALL

On Mon, Sep 27, 2010 at 10:10:40AM -0700, Linus Torvalds wrote:
> On Mon, Sep 27, 2010 at 9:26 AM, Ivan Kokshaysky
> <ink@...assic.park.msu.ru> wrote:
> >
> > Looks like we need to drop HAE bits from SAVE_ALL/RESTORE_ALL, which
> > benefits (1) and automatically fixes (3), and do the entire IO sequences
> > in (2) with disabled interrupts (if HAE is involved).
> 
> No can do.
> 
> HAE is used in user space too (the X server), and it depends on the
> kernel restoring HAE over interrupts and system calls, afaik.
> 
> I'm also pretty certain that all SMP machines either don't have HAE at
> all, or have a per-CPU HAE in hardware (and then it's possible that we
> screw it up in software, of course). Anything else would be too broken
> for words. Can somebody find documentation saying otherwise?

Besides, I'm not particulary happy to force a couple of swpipl on each
iomem access on old UP alpha boxen.

The only flavours that have HAE at all are APECS, LCA, MCPCIA, JENSEN and
T2.  APECS, LCA and JENSEN are UP-only, MCPCIA we build with
MCPCIA_ONE_HAE_WINDOW which blocks HAE switching AFAICS.  So it's really
about T2 and there we have something interesting:

#define T2_HAE_1                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
#define T2_HAE_2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
#define T2_HAE_3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
#define T2_HAE_4                (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
#define T2_HAE_ADDRESS          T2_HAE_1

And seeing that it appears to be 4-CPU chipset...
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