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Message-ID: <20100929150253.GB9440@lenovo>
Date: Wed, 29 Sep 2010 19:02:54 +0400
From: Cyrill Gorcunov <gorcunov@...il.com>
To: Stephane Eranian <eranian@...gle.com>
Cc: Robert Richter <robert.richter@....com>,
"mingo@...hat.com" <mingo@...hat.com>,
"hpa@...or.com" <hpa@...or.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"yinghai@...nel.org" <yinghai@...nel.org>,
"andi@...stfloor.org" <andi@...stfloor.org>,
"peterz@...radead.org" <peterz@...radead.org>,
"ying.huang@...el.com" <ying.huang@...el.com>,
"fweisbec@...il.com" <fweisbec@...il.com>,
"ming.m.lin@...el.com" <ming.m.lin@...el.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"dzickus@...hat.com" <dzickus@...hat.com>,
"mingo@...e.hu" <mingo@...e.hu>
Subject: Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after
disabling counters
On Wed, Sep 29, 2010 at 03:56:08PM +0200, Stephane Eranian wrote:
...
> Ok, I think we agree on this. It is handled in the Intel case, though it
> is not clearly explained with a comment.
> The P4 case needs to be fixed.
>
Seems so. Thanks Stephane. I'll check and fix as only be able to
(in a couple of hours).
Cyrill
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