linux-kernel - Re: [PATCH -v2 6/7] x86, NMI, Add support to notify hardware error with unknown NMI

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Message-ID: <alpine.LFD.2.00.1010012027360.21189@eddie.linux-mips.org>
Date:	Fri, 1 Oct 2010 21:00:08 +0100 (BST)
From:	"Maciej W. Rozycki" <macro@...ux-mips.org>
To:	Huang Ying <ying.huang@...el.com>
cc:	Don Zickus <dzickus@...hat.com>,
	huang ying <huang.ying.caritas@...il.com>,
	Robert Richter <robert.richter@....com>,
	Ingo Molnar <mingo@...e.hu>, "H. Peter Anvin" <hpa@...or.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Andi Kleen <andi@...stfloor.org>
Subject: Re: [PATCH -v2 6/7] x86, NMI, Add support to notify hardware error
 with unknown NMI

On Thu, 30 Sep 2010, Huang Ying wrote:

> > Is port 0x61 architectural?  I thought it a southbridge thing.  In fact I
> > thought with modern chipsets you can access the same thing through port
> > 0x70 or 0x71 (I can't seem to figure out which Intel doc I saw that in).
> > (Not that this conversation has any bearing on your patchset, just an idea
> > I had).
> 
> At least until now, I think port 0x61 can be considered architectural
> (just like we think PIT is architectural before). Maybe in the future it
> will become deprecated and turned into something like a device driver.
> But why not wait until it be.

 This port-mapped I/O register has been first defined by IBM back in 1981 
with their original PC and its 8255 PPI whose port A (at 0x60) served as a 
keyboard interface chip and the remaining ports B (0x61) and C (0x62) were 
used as GPIO (there was also a control register at 0x63, whose purpose was 
to configure the ports; the PPI was a general-purpose chip).  The 
arrangement remained the same with the PC/XT (with the tape recorder 
interface removed ;) ).

 That functionality was then slightly modified and carried over to their 
PC/AT where the functionality previously provided by 8255's port A and 
some GPIO was replaced with an 8042 microcontroller and the remaining GPIO 
was implemented with some discrete glue logic.  With time, as technology 
advanced, that logic was carried over to integrated ASICs like the Intel 
82357 Integrated System Peripheral (ISP) and eventually, with the advent 
of PCI, to the south bridge, alongside all the legacy PC/AT motherboard 
junk I/O (though a discrete 8042 has remained common; these days hanging 
off the LPC bus).

 I am fairly sure you can consider the NMI status register at 0x61 a 
standard cast in stone and I don't think you'll ever find a workstation 
x86 system without one (it also controls the binary speaker, BTW), though 
obviously its presence may vary across embedded x86 systems.  Things may 
of course eventually change if some company decides (and Intel would 
certainly seem capable enough) to get rid of some legacy junk.  I would 
start with getting rid of the 8259A pair first though.

  Maciej
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