linux-kernel - Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after disabling counters

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Date:	Sat, 2 Oct 2010 19:40:08 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Robert Richter <robert.richter@....com>
Cc:	"mingo@...hat.com" <mingo@...hat.com>,
	"hpa@...or.com" <hpa@...or.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"yinghai@...nel.org" <yinghai@...nel.org>,
	"andi@...stfloor.org" <andi@...stfloor.org>,
	"peterz@...radead.org" <peterz@...radead.org>,
	"gorcunov@...il.com" <gorcunov@...il.com>,
	"ying.huang@...el.com" <ying.huang@...el.com>,
	"fweisbec@...il.com" <fweisbec@...il.com>,
	"ming.m.lin@...el.com" <ming.m.lin@...el.com>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"dzickus@...hat.com" <dzickus@...hat.com>,
	"mingo@...e.hu" <mingo@...e.hu>
Subject: Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after
 disabling counters

On Sat, Oct 2, 2010 at 11:50 AM, Robert Richter <robert.richter@....com> wrote:
> On 29.09.10 10:00:54, Stephane Eranian wrote:
>
>> > Here is another difference I noticed in x86_handle_irq() vs.
>> > intel_pmu_handle_irq().
>> > For Intel, handled is incremented even if there is no 64-bit overflow.
>> >
>> > With generic X86, it is incremented only when you have a 64-bit
>> > overflow. I think that's wrong. You don't hit that condition very often
>> > on AMD because counters are 47 bits wide, but this is generic code
>> > and on P6 you definitively will. I believe you need to hoist handled++
>> > just after the check on active_mask.
>> >
>> >
>> > What do you think?
>> >
>> In other words, I think handled is there to track interrupts, i.e., hw
>> counter overflows, and not 64-bit software counter overflows (which
>> do trigger sample recording).
>
> Stephane, the code looks good. We must first read the counter msr, its
> raw value is returned by x86_perf_event_update(). Then we check we MSB
> of the *counter* value and if it is zero, we detected a counter
> overflow (not a 64 bit overflow) and increment 'handled'.
>
Yes, you are right. I double-checked that again Friday and the code is
okay for Intel, generic X86 and P4.
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