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Message-ID: <AANLkTikPpE+ewz5NUVRV5ASdGv+a=ZxHnckfUaWs-KCD@mail.gmail.com>
Date: Mon, 4 Oct 2010 19:28:42 +0200
From: Stephane Eranian <eranian@...gle.com>
To: Andi Kleen <andi@...stfloor.org>
Cc: Robert Richter <robert.richter@....com>,
Huang Ying <ying.huang@...el.com>,
Don Zickus <dzickus@...hat.com>,
Cyrill Gorcunov <gorcunov@...il.com>,
"mingo@...hat.com" <mingo@...hat.com>,
"hpa@...or.com" <hpa@...or.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"yinghai@...nel.org" <yinghai@...nel.org>,
"peterz@...radead.org" <peterz@...radead.org>,
"fweisbec@...il.com" <fweisbec@...il.com>,
"ming.m.lin@...el.com" <ming.m.lin@...el.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...e.hu" <mingo@...e.hu>
Subject: Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after
disabling counters
Andi,
On Mon, Oct 4, 2010 at 11:07 AM, Andi Kleen <andi@...stfloor.org> wrote:
>> I haven't seen Andi's suggestion. But I am guessing he is suggesting
>> adding a new chain that would be called first and where there would
>> ONLY be the perf_event subsystem. To handle the spurious PMU
>
> I was thinking of a separate NMI chain
>
You mean separate callbacks which rely on getting an NMI interrupt
from those which don't? If so, I definitively agree with you on that.
> (and longer term really splitting the die chains into separate chains,
> that would solve other problems e.g. with page fault performance
> too)
>
> Possibly that NMI chain could be split up too, but not sure
> this is really needed.
>
You need to split to enforce more explicit priority scheme than what
you have today with an ordered list per chain.
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